RE: [sv-bc] name resolution of struct members

I think the case Francoise is talking about is like this one:

typedef struct { int d; } ST1;
typedef struct { ST1 b; } ST2;

module m1();
logic c;
endmodule

module m2();
m1 b();
endmodule

module child();
ST2 a;
initial a.b.c = 0;
endmodule

module top();
m2 a();
child u1();
endmodule

Here 'a.b.c' can not be completely resolved as a struct field reference
starting from the struct variable 'a' in module 'child', but there is a
upward resolution as a hierarchical name starting from the instance 'a'
of module 'm2' in the module 'top'.
 
I believe this should follow the Verilog hierarchical name resolution
rules, where a struct variable in the local module is treated the
same as a module instance in the local module.

In this case there is a struct variable 'a' in the module 'child', so
this should be treated like a downward reference.

The 1364-2001 LRM says in section 12.5 say:

<quote>
Upwards name references can also be done with names of the form

            module_instance_name.item_name

A name of this form shall be resolved as follows:

a) Look in the current module for a module instance named
module_instance_name. If found, this name reference shall be
treated as a downward reference, and the item name shall be
resolved in the corresponding module.

b) Look in the parent module for a module instance named
module_instance_name. If found, the item name shall be resolved
from that instance, which is the sibling of the module containing
the reference.

c) Repeat step b), going up the hierarchy.
</quote>

I believe that rule a above means that 'a.b.c' in the above example
is an error.

I had heard that the IEEE Errata committee was looking at some open
questions in hierarchical name resolution, and I do not currently have
access to that information. I thought it was only related to issues with
hierarchical names resolution and generate unrolling.

> I could not find in the systemVerilog draft 6 anything that describes
> enhanced name resolution rules.
> A struct member name uses the . separator that is also used for
> hierarchical names.
> So it appears that we need to take this into account when doing name
> resolution.
> Currently in Verilog, if a . name is found we do downward and upward name
> lookup trying to resolve the XMR.
>
> So if I have a name "a.b.c" in a given scope and I have a struct variable
> named "a" in that scope which has a "b" member which does not contain a "c"
> member, is this a parser error because the trial failed or do we assume
> that this is an XMR which will be resolved when the whole design is elaborated?
>
> Francoise
> '
Received on Wed Apr 7 15:37:38 2004