Re: [sv-bc] replication in array literal


Subject: Re: [sv-bc] replication in array literal
From: Paul Graham (pgraham@cadence.com)
Date: Tue Jan 06 2004 - 13:40:19 PST


> Your final example would have to be
>
> bit x [3:0] = { 3:a, 2:b, default:y };
>
> since you cannot mix positional values with a default label.

By the way, what is the reason for this restriction? In vhdl you can (and
often do) write an array aggregate like (1, 2, others => 3). I see that
you generally don't want to mix named and positional association, but this
example seems easy to handle.

Paul



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