Re: [sv-bc] replication in array literal


Subject: Re: [sv-bc] replication in array literal
From: Dave Rich (David.Rich@synopsys.com)
Date: Mon Jan 05 2004 - 13:36:57 PST


Paul,

This is a limitation the way it is currently written. The braces must
match the array layout. Your final example would have to be

 bit x [3:0] = { 3:a, 2:b, default:y };

since you cannot mix positional values with a default label.

Dave

Paul Graham wrote:

>I'm running into an ambiguity or limitation of the replication operator
>when used in an array literal.
>
>Section 7.13 defines the replication operator with this example:
>
> unpackedbits = {2 {y}} ; // same as {y, y}
>
>Suppose I have:
>
> bit x [3:0] = { a, b, y, y };
>
>Perhaps I'd like to avoid writing out the two y's, and use:
>
> bit x [3:0] = { a, b, {2{y}} };
>
>However, this is said to be equivalent to:
>
> bit x [3:0] = { a, b, {y, y} };
>
>which is not legal in an array literal context, because it introduces an
>extra level of braces which does not match the array type structure.
>
>As currently defined, a replication can only be used within an array literal
>when the replication stands alone as a complete sub-array within the array
>literal, for instance:
>
> bit x [2:0][3:0] = { {4{a}}, {4{b}}, {4{c}} };
>
>I'd like to verify that this is the intent of the LRM.
>
>BTW, my original example can be written using the default keyword:
>
> bit x [3:0] = { a, b, defualt:y };
>
>but there can only be one default per array literal, which limits its
>usefulness.
>
>Happy new year, everyone!
>
>Paul
>
>
>
>

-- 
--
David.Rich@Synopsys.com
Technical Marketing Consultant
http://www.SystemVerilog.org
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