[sv-bc] Proposal for SV-BC-95


Subject: [sv-bc] Proposal for SV-BC-95
From: Dave Rich (David.Rich@synopsys.com)
Date: Sun Nov 16 2003 - 23:38:55 PST


This is a proposal for SV-BC-95. Note that BC-108 is a duplicate of this issue.

REPLACE section 19.8 Access without ports

WITH (keywords in bold)

19.8 Access to Interface objects

Access to all objects declared in an interface is always available by hierarchical reference, regardless of whether or not the interface is connected through a port. When an interface is connected with a modport in either the module header or port connection, access  by port reference is limited to only those objects listed in the modport, for only those types of objects legal to be listed in modports (wires, variables, tasks, and functions) All objects are still visible by hierarchical reference. For example:

interface ebus_i;
  integer I;	// reference to I not allowed through modport mp
  typedef enum {Y,N} choice;
  choice Q;
  parameter True = 1;
  modport mp(input Q);
endinterface
module Top;
  ebus_i ebus;
  sub s1(ebus.mod);
endmodule
module sub(interface.mp i);
  typedef i.choice yes_no; 	// import type from interface
  yes_no P;
  assign P = i.Q;		// refer to Q with a port reference
  initial
	Top.s1.Q = True; 	// refer to Q with a hierarchical reference
  initial
	Top.s1.I = 0; // refering to i.I would not be legal because is not in modport mp
endmodule


--
David.Rich@Synopsys.com
Technical Marketing Consultant
http://www.SystemVerilog.org
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