[sv-bc] RE: Connecting generated interface instances

The LRM says in 25.3,

"If the actual of an interface port connection is a hierarchical reference to an interface ..., the hierarchical reference shall refer to an interface instance and shall not resolve through ... a generate block."

What is the reason for this restriction ?

Example:

///////////////////// Beginning of code ///////////////////////

interface if1 ();
endinterface

module module1 (if1 if1_inst);
endmodule

module test();
      generate
            for (genvar i=0; i<2; i++) begin : if_gen
                  if1 if1_inst();
            end
      endgenerate

      module1 module1_inst
            (
            .if1_inst(if_gen[0].if1_inst)
            );

endmodule

//////////////////////// End of code /////////////////////////

I saw 2 major compilers reject this code due to the above restriction.

Thanks,
Shalom
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Intel Israel (74) Limited

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