>Stu: [...] Implementations have created unique x-propagation semantics.> >Shows LRM x-propagation semantics insufficient. >Would like to see one semantic standardized. >Stu offered to be a champion of x-propagation [...] Stu has been doing some great work lately ( https://bradpierce.wordpress.com/2014/10/07/dont-use-x-assignments-to-make-systemverilog-case-statements-more-pessimistic ) on how to cope with 'X' as traditionally defined in Verilog, but I speculate that a root cause is that the traditional Verilog definition is not nuanced enough. For example, an explicit 'X' assignment in a case default is sometimes used to mean don't-care (such as when the value only matters when a flag has been raised), and sometimes used to mean badness (such as in a unique-case because the LRM says that otherwise the variable holds its value after a violation). And both of those concepts are distinct from uninitialized and from don't-know (such as when a net has been temporarily connected to a black-box). So part of the right fix might be to enhance beyond 4-state logic and instead of lumping all of these concepts together as 'X', distinguish them and enhance the rules to propagate each in their own appropriate way. I also think the definition of out-of-bounds array write, especially for an 'X' index, deserves some special attention, because in practice it seems to be the 'X' issue that causes the most dismay. -- Brad [In reply to http://www.eda.org/sv-bc/hm/11692.html / http://www.eda.org/sv-ec/hm/8568.html ] -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Sat Feb 21 11:27:40 2015
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