[sv-bc] RE: Query related with signedness of an expression.

In this case, var1 is unsigned.  A single element of var1, such as var1[0], is of type reg2 and is signed.  But var1 was not declared as signed, so it is unsigned.  In fact, there is no way to declare it to be signed.  The declaration grammar only allows you to declare one of the array levels to be signed.  This is a deficiency in the language, but that is how it was defined.  For a discussion of this deficiency, see

http://www.eda.org/svdb/view.php?id=1291


From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of Dhiraj Kumar Prasad
Sent: Friday, November 16, 2012 3:27 AM
To: sv-bc@eda.org
Cc: Dhiraj Kumar Prasad
Subject: [sv-bc] Query related with signedness of an expression.

Hello,

I have an query related with signedness of the expression.

Please see the following example

module top(output reg [7:0] out1);

typedef reg signed [1:0] reg2;
typedef reg2 [1:0] reg4;

reg4 var1;

always_comb
begin
        var1 = '1;
        out1 = var1;
end
endmodule

Here the var1 should be treated as signed or unsigned. I am seeing the different result in different standard tools. Some tool's are assigning out1 with 8'b11111111 (treated as signed) while some other tools are assigning out1 with 8'b00001111.

So my query is should var1 be treated as signed or unsigned ??

Regards,
dhiRAj


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