[sv-bc] Query related with signedness of an expression.

Hello,

I have an query related with signedness of the expression.

Please see the following example

module top(output reg [7:0] out1);

typedef reg signed [1:0] reg2;
typedef reg2 [1:0] reg4;

reg4 var1;

always_comb
begin
        var1 = '1;
        out1 = var1;
end
endmodule

Here the var1 should be treated as signed or unsigned. I am seeing the different result in different standard tools. Some tool's are assigning out1 with 8'b11111111 (treated as signed) while some other tools are assigning out1 with 8'b00001111.

So my query is should var1 be treated as signed or unsigned ??

Regards,
dhiRAj


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