[sv-bc] RE: Agenda: May 10 SV-BC Meeting

From: Bresticker, Shalom <shalom.bresticker@intel.com>
Date: Sun May 09 2010 - 12:29:26 PDT

Gord approved to send the paper, attached.

Shalom

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On
> Behalf Of Bresticker, Shalom
> Sent: Sunday, May 09, 2010 9:56 AM
> To: Maidment, Matthew R; sv-bc@eda.org
> Subject: [sv-bc] RE: Agenda: May 10 SV-BC Meeting
>
> The DVCON 2009 interface paper was called, "Is There a Future
> for SystemVerilog Interfaces?"
>
> Abstract:
> The SystemVerilog interface is intended to be a powerful
> modeling construct for describing hardware interconnect in a
> very general manner that is applicable to both testbench and
> synthesizable RTL design applications. In this paper we argue
> that the SystemVerilog interface construct is inadequately
> specified, insufficiently powerful for real applications, and
> impossible to implement consistently in its current form. We
> then review the application areas that interfaces were
> intended to address, and propose some possible solutions for
> these shortcomings.
>
> It can be requested at
> http://www.mentor.com/products/fv/techpubs/is-there-a-future-f
> or-systemverilog-interfaces--49113 or
> http://www.techonline.com/learning/techpaper/217701248
>
> If Mentor has no objections, I can post it directly to the reflector.
>
> Shalom
>
>
> > Outstanding
> 04/26/10 Gord or anyone else provide URL or copy of
> interface paper if
> publicly available.
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Received on Sun May 9 12:29:59 2010

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