RE: [sv-bc] expressions not allowed in RHS or continous assign or on port connection list

John,

This is not a problem because a function is made up of procedural
statements, creating a procedural context. It is up to the user to make
sure the function does not have any undesired side-effects.

However, if you put an assignment operator within a continuous
assignment (explicit statement or implicit context), there would be no
way for the user to control the outcome of that assignment since
implementations can execute it an indeterminate number of times.

Dave

> -----Original Message-----
> From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org] On Behalf Of
John
> Michael Williams
> Sent: Wednesday, April 07, 2010 2:53 PM
> To: sv-bc@eda.org
> Subject: Re: [sv-bc] expressions not allowed in RHS or continous
assign
> or on port connection list
>
> Hi.
>
> This may be a problem, because function calls are permitted in
> continuous assignment statements in verilog.
>
> On 04/07/2010 07:51 AM, Brad Pierce wrote:
> > "It shall be illegal to include an assignment operator ... in an
> > expression that is not within a procedural statement."
> >
> > On Wed, Apr 7, 2010 at 7:43 AM, Daniel Mlynek
> > <daniel.mlynek@aldec.com.pl> wrote:
> >> I cannot find in LRM resrtictions on expression on RHS of
continuous
> assign
> >> (same for port connection list items).
> >> IMO some expressions should not be allowed ie:
> >> assign w = i++;
> >> assign w = i=+10;
> >> assign w = foo(i); //where foo is function foo (ouput logic o);
o=o-1;
> >> endfunction
> >>
> >> same for port connections:
> >> sub uut(i++);
> >> sub uut(i=+10);
> >> sub uut(foo(i)); //where foo is function foo (ouput logic o);
o=o-1;
> >> endfunction
> >>
> >>
> >> Should it be allowed or forbidden?
> >> Is it described in LRM?
> >>
> >>
> >> DANiel
> >> --
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>
> --
> John Michael Williams
> Senior Adjunct Faculty
> Silicon Valley Technical Institute
>
> --
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