Subject: [sv-bc] RE: SystemVerilog 3.1 Is An Accellera Standard
From: Vassilios.Gerousis@Infineon.Com
Date: Thu May 29 2003 - 13:13:32 PDT
Correction!
> -----Original Message-----
> From: Gerousis Vassilios (CL DAT CS)
> Sent: Thursday, May 29, 2003 10:10 PM
> To: 'sv-ac@eda.org'; 'sv-bc@eda.org'; 'sv-cc@eda.org'; 'sv-ec@eda.org'
> Subject: SystemVerilog 3.1 Is An Accellera Standard
> Importance: High
>
> Dear SV chairs, champions and all SV members,
> It is a pleasure to announce to everyone that Accellera Board has
> approved SystemVerilog 3.1 on May 29, 2003. It is now a formal Accellera
> standard where users and EDA vendors can now start building tools and
> designs using this great technology. The following companies voted against
> SystemVerilog (Cadence and Verplex). Verisity abstained.
> I want to thank everyone who worked hard in the development of this
> new standard. We will take the next few weeks to relax. We will come back
> in few weeks to discuss the next steps.
>
> Best Regards
>
> Vassilios
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