Subject: [sv-bc] SystemVerilog 3.1 Is An Accellera Standard
From: Vassilios.Gerousis@Infineon.Com
Date: Thu May 29 2003 - 13:09:48 PDT
Dear SV chairs, champions and all SV members,
It is a pleasure to announce to everyone that Accellera Board has
approved SystemVerilog 3.1 on May 29, 2003. It is not a formal Accellera
standard where users and EDA vendors can now start building tools and
designs using this great technology. The following companies voted against
SystemVerilog (Cadence and Verplex). Verisity abstained.
I want to thank everyone who worked hard in the development of this
new standard. We will take the next few weeks to relax. We will come back in
few weeks to discuss the next steps.
Best Regards
Vassilios
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