Re: [sv-bc] Re: Post 3.1


Subject: Re: [sv-bc] Re: Post 3.1
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Thu May 08 2003 - 10:30:05 PDT


I previously posted suggesting that we could reduce the size of the
language and get better backward compatibility by reimplementing stuff
as typedefs in standard header files. It occured to me that you could
also do it by using pre-defined typedefs if you add an "untypedef"
capability. E.g. if you have bit & logic predefined (as per previous
discussion with Cliff) -

  typedef unresolved_bit bit;
  typedef resolved_bit logic;

- then you could do something like:

  untypedef bit;
  untypedef logic;
  `include "my_old_verilog.v" // old code using "bit" or "logic"

You could consider "byte","short" & "int" as being:
   
  typedef signed unresolved_bit [7:0] byte;
  typedef signed unresolved_bit [15:0] short;
  typedef signed unresolved_bit [31:0] int;

Just a thought,
Kev.

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