Subject: [sv-bc] RE: LRM Draft 4 issues
From: David W. Smith (david.smith@synopsys.com)
Date: Wed Apr 09 2003 - 09:54:07 PDT
Yes. Just getting to them. They are next on my plate.
Regards
David
-----Original Message-----
From: Dave Rich [mailto:David.Rich@synopsys.com]
Sent: Monday, April 07, 2003 10:44 AM
To: David W. Smith; sv-bc@eda.org
Subject: LRM Draft 4 issues
LRM-2 LRM-3
I don't see the confusion here. "formals" are created in the definition
of a body, "actuals" are what is used in the reference of that body. So
actual parameters are what is used when instantiating a module. For example
module foo
(input bit A); // formal port A
parameter B=2; // formal parameter B
task C
(input bit D); // formal argument D
endtask
endmodule
module top;
bit X;
foo
#(3) // actual parameter 3 for formal B
I (X); // actual port X for formal A
initial I.C
(X+1); // actual argument X+1 for formal D
endmodule
LRM-4 LRM-9
BC65 superseded BC62a. Should have used BC65
See http://www.eda.org/sv-bc/hm/0592.html for an explanation
LRM-5
7.13 is correct
LRM-6
3.4.1 was from the SV3.0
This is now just section 3.4 in draft4
See http://www.eda.org/sv-bc/hm/0422.html for an explanation
LRM-25
Suggest globally replacing .name with .port_identifier in italics.
LRM-26
This was supposed to be in a proposal for SV21-1, which got pushed to
SV3.2. We are going to have to replace that with something else. See
http://www.eda.org/sv-bc/hm/0580.html for an explanation.
-- -- Dave Rich Principal Engineer, CAE, VTG Tel: 650-584-4026 Cell: 510-589-2625 DaveR@Synopsys.com
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