Subject: Re: [sv-bc] Tasks with null statement (;) as body
From: Brad Pierce (Brad.Pierce@synopsys.com)
Date: Thu Mar 13 2003 - 15:10:28 PST
This issue can be closed if the proposal for SV-BC69 is passed.
-- Brad
-----Original Message-----
From: owner-sv-bc@eda.org [mailto:owner-sv-bc@eda.org]On Behalf Of Brad
Pierce
Sent: Thursday, March 13, 2003 2:23 PM
To: sv-bc@eda.org
Subject: [sv-bc] Tasks with null statement (;) as body
An issue to be deferred until 3.2, is that SystemVerilog is now out
of sync with the 1364 ETF/VSG regarding task declarations --
http://www.boyd.com/1364_btf/report/full_pr/65.html
If SystemVerilog is to be a superset of Verilog, then it must allow
the following --
module m;
task t;
;
endtask
endmodule
even though, unlike Verilog, SystemVerilog accepts the more natural
module m;
task t;
endtask
endmodule
and even though Verilog and SystemVerilog both allow
module m;
task t;
begin end
endtask
endmodule
-- Brad
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