Subject: Re: [sv-bc] Fwd: RE: Slice with unpacked arrays
From: Kevin Cameron x3251 (Kevin.Cameron@nsc.com)
Date: Tue Feb 04 2003 - 11:05:26 PST
> From owner-sv-bc@server.eda.org Tue Feb 4 01:42:30 2003
> From: "Dave Rich" <David.Rich@synopsys.com>
> Organization: Synopsys VTG
> X-Accept-Language: en-us, en
> To: "Karen Pieper" <Karen.Pieper@synopsys.com>
> cc: sv-bc@server.eda.org
> Subject: Re: [sv-bc] Fwd: RE: Slice with unpacked arrays
>
> So here is my understanding of the issues from todays CC and a set of proposals.
> Please respond to this via with positive or negative feedback so I can refine my proposal into something that we can vote on quickly.
>
> Basically, the issues are not really with slices, but in the definition of literals. Although we did not discuss it, these issues are there for structure literals too.
>
> First, SystemVerilog allows the use of literals in non-initial assignment statements. Since Verilog already had a syntacticly similar concat operation, it allows similar replication operation in literals. These facts are presented in the 3.0 LRM and further clarified by SV-BC7b.
>
> Second, the spec creates confusion in these places:
>
> a. The term "literal" typically means a constant, and "array literal" usually implies its use as an initializer only. Note that C does not use the term "literal", and instead just uses the term "initializer"
>
> b. The examples show only constants in literals.
>
> c. The BNF makes no distinction between literals and concatenation. The LRM provides a casting operation when the context is ambiguous, but does not define what is or is not ambiguous.
>
> And Third, once all the confusion with the second issue gets cleared up, it will be trivial to define the slice of an unpacked array in terms of the syntactic sugar that represents the individual elements of the array.
>
> So here are my proposals:
>
> Take existing Verilog concatenations and call them "packed concatenations". Recall that a packed concatenation is a just list of "packable" elements.
>
> Rename Array literals to "unpacked concatenations". An unpacked concatenation is a list of elements that match the type, size and shape of an existing unpacked type. An unpacked concatenation may be used wherever an expression of that matching unpacked type is legal (meaning for copy or compare)
>
> SystemVerilog determines if a concatenation is packed or unpacked by looking at the LHS type of an assignment statement. Concatenations not on the RHS of an assignment are assumed to be packed, unless cast to unpacked with "type'{...}".
Are you including assignment in declarations?
If your LHS is a packed struct/array can you still tell?
Would it be easier to say all unpacked concatenations need to be cast?
Kev.
> Unpacked concatenations are not legal on the LHS of an assignment statement. (Making them legal would introduce ambiguities, plus casting on the LHS is not legal)
>
>
> Dave
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