Subject: December 4 - SystemVerilog Full Committee Slides
From: Vassilios.Gerousis@Infineon.Com
Date: Sun Dec 08 2002 - 15:06:42 PST
Dear SV members,
We are on schedule based on the milestones that we have put together
for delivery of
SystemVerilog 3.1 LRM. Thanks to Sutherland, we have assembled the first
draft (draft1). Every committee is on track in terms of milestones
achievements. You will find all the slides presented
in our face to face meeting in this email.
1- SV-AC Committee status and Assertion Language update.
2- SV-BC Committee status (will be sent later).
3- SV-EC Committee status and language update.
4- SV-CC committee status and technical update.
5- SV status, patent and LRM update.
6- Peter Flake and his technical team Technical Updates on SystemVerilog 3.1
Semantics and scheduling.
I want to thank everyone who participated. Thanks for Joe for taking
the minutes. Jay Lawrence has sent his slides to the group already.
<<SV-December20023-Slides.zip>>
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Dr. Vassilios Gerousis
Chief Scientist
Infineon Technologies
DAT CS, MchB
D-81541 Munich
Germany
BalanSt. 73
Telephone: +49-89-234-21342
Fax: +49-89-234-23650
email: Vassilios.Gerousis@infineon.com
Site Map:
http://www.stadtplandienst.de/query;ORT=m;PLZ=81541;STR=Balanstr%2E;HNR=73
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