Subject: Fwd: Another small errata in the System Verilog 3.0 BNF
From: Karen Pieper (Karen.Pieper@synopsys.com)
Date: Fri Oct 04 2002 - 17:28:50 PDT
>From: "Jacobi, Dan" <dan.jacobi@intel.com>
>To: Karen.Pieper@synopsys.COM
>Subject: Another small errata in the System Verilog 3.0 BNF
>Date: Thu, 3 Oct 2002 16:32:10 +0300
>X-Mailer: Internet Mail Service (5.5.2653.19)
>
>Karen,
>
>A cow-worker of mine has found another small errata in the System-Verilog
>3.0 BNF regarding the modports of interfaces
>
>quoting part of the BNF from page 98 under sub-bullet A.2.9 :
>modport_port ::=
> input [port_type] port_identifier
> | output [port_type] port_identifier
> | inout [port_type] port_identifier
> | interface_identifier . port_identifier
> | import_export task named_task_proto
> | import_export function named_fn_proto
>
>It looks like the rule
> modport_port ::= interface_identifier . port_identifier
>should be replaced with the following rule
> modport_port ::= interface_identifier .modport_identifier
>( Replacing the port_identifier token with the modport_identifier token)
>This will enable parsing of such RTLs (Based on the example at the end of
>page 70) :
> interface i1;
> interface i3;
> wire a, b, c, d;
> modport master (input a, b, output c, d);
> modport slave (output a, b, input c, d);
> endinterface
> i3 ch1(), ch2();
> modport master2 (ch1.master, ch2.master);
> endinterface
>Please note that the original example from the System-Verilog 3.0 LRM has a
>small errata - the brackets near the interface instantiation are missing (I
>don't think I mentioned this example in my previous E-mail)
>
>Thanks Again,
>Danny
>
>
>Dan Jacobi - Intel corporation
>Office Tel : (972) - 4 - 8655855
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