your review of SystemVerilog 3.0 LRM

Subject: your review of SystemVerilog 3.0 LRM
From: Shalom Bresticker (Shalom.Bresticker@motorola.com)
Date: Mon Sep 30 2002 - 05:26:07 PDT

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Hi, Dan.

I started looking through your comments on the SystemVerilog 3.0 LRM,
on the comments which are relevant to IEEE 1364-2001.

Some of your comments are already known to us, some are new.
Congratulations.

Item 3: Table 7-2 missing "^~": you seem correct.

Item 6: BNF:
A.1.1, A.1.2 redundant square brackets - you seem correct.
The same comment seems applicable in A.9.4 to simple_hierarchial_branch
and escaped_hierarchial_branch.

A.1.1 include_statement: You say, "A back tic should come before the
include directive."
This is incorrect. This is an include statement, added in 1364-2001, not
the `include
compiler directive. It does not have a back tic.

I'll try to keep you updated.

Thanks,
Shalom

--
Shalom Bresticker                           Shalom.Bresticker@motorola.com
Design & Reuse Methodology                             Tel: +972 9 9522268
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"The devil is in the details."

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