IEEE P1364.1 Verilog Synthesis Interoperability Working Group
Conference Call Minutes
July 6, 2001

Minutes taken by Ken Coffman
Send comments and corrections to kcoffman@sos.net

Callers:
J. Bhasker
Joe Wetstein
Stephen Boyd
Cliff Cummings
Ben Cohen
Ken Coffman
JenJen Tiao
Sashi Obilisetty

•	Cliff  Cummings: The IEEE-2001 Verilog LRM should be published by September 2001. 
•	Draft 1.6 of the RTL Synthesis standard is posted at www.eda.org/vlog-synth
•	In the absence of another volunteer, Bhasker will continue to be the central document coordinator. We need a volunteer though.
•	Joe Wetstein: Verilog-2000 logical and arithmetic shift operators should be synthesizable.
•	Joe Wetstein: (* rtl_synthesis, full_case *) and (* rtl_synthesis, full_case, parallel_case *) should be added as examples of attribute usage. The funny braces replace pseudo-comments so vendors don’t have to parse comment fields. There is some discussion about the attribute format, rtl_synthesis_full_case, or rtl_synthesis_full_case = true, or rtl_synthesis_full_case = 1 and comma separators for multiple attributes.
•	PraveenTiwari (Bhasker reported): More discussion is required regarding whether the LHS of an assignment should permit +: index ranges with a variable range per Praveen’s email. Vector part select in both first and second ranges? Fully supported for RHS, how about LHS? This can be implemented with decoder, so it should be synthesizable. This should be used only for small vectors. As long as the index is resolved, the full range should be supported.
•	Praveen Tiwari (Bhasker reported): Re-entrant Tasks and Functions. As long as these can be fully elaborated, they should be synthesizable. Cadence and Mentor (ModelSim) said “yuck” to re-entrant tasks. Synopsys says they will support and Tekronix (internal tool) supports.
•	There are three forms of generate: loop, condition, and case. Elaboration should occur before synthesis, this works in VHDL.  Generate should be fully supported for synthesis.
•	Multi-dimensional arrays, scalars and vectors. Format: foo[<range> ] [<range> ] The next rev of VHDL (2003?) will support this. Bit/part of arrays allowed. We should point out that initializing memory bits and multiple addresses is a problem for hardware. Bit addressing for register arrays is ok.
•	New sys task/functions are not supported. File I/O not required for synthesis, but would be desirable for initializing RAMs and register power-up conditions in initial block (FPGAs allow selecting flipflop power up states and RAM content). Allow readmemh and readmemv in Initial block?
•	Cliff Cummings: @* and comma-separated sensitivity lists are supported.
•	Should coding styles be part of document body or in an annex?
•	Suggestion to add memory styles to Section 5 (or annex if examples are moved). Memory styles include ROM (combinational logic), synchronous RAM, asynchronous RAM (latches). We may want to give specific control: (*reg*), (*ram*), or (*latch*). Ben & Cliff (and anyone else) will exchange group e-mail regarding RAM and ROM syntax and examples.
•	The next conference call is scheduled for August 10th.