This document lists the new Verilog 2001 features and 
suggests to its synthesizability:


FEATURE						SYNTHESIZABLE?
-------						--------------

 1. Generate block (for, ifelse, case)		Yes

 2. Multidimensional arrays			Yes

 3. Bit and part-select with arrays		Yes

 4. Enhanced file I/O				No

 5. Re-entrant tasks and functions		Yes; recursion with static bnd

 6. Configuration block				Yes

 7. Library map files				Yes

 8. Named parameter association			Yes

 9. Comma sep sensitivity list			Yes

10. Event symbol @*				Yes

11. ANSI style I/O decls			Yes

12. Automatic width extension beyond 32 bits	Yes

13. Indexed part select				Yes

14. Reg initial declaration			No 

15. Signed type					Yes

16. System functions $signed, $unsigned		Yes

17. Constant functions				Yes

18. Addtl cond compilation(`ifndef,`elsif,`undef) Yes

19. Power op (**)				Yes - first operand is 2, or 
						opds are constants.

20. 'line compiler directive			Yes (ignored)

21. Arithmetic shift ops (<<<, >>>)		Yes

22. Combined port and data type decl		Yes

23. Parallel case attribute			Yes 
    (* rtl_synthesis_parallel_case *)

24. Full case attribute				Yes
    (* rtl_synthesis_full_case *)

25. On-detect pulse error propogation		No
    (pulsestyle_onevent, pulsestyle_ondetect)

26. Negative pulse detection			No
    (showcancelled, noshowcancelled)

27. New timing checks				No
    ($removal, $recrem, $timeskew, $fullskew)

28. Negative timing constraint			No
    (modified $setuphold)

29. New VCD system tasks			No

------------------------
   
- J. Bhasker, June 1, 2001