Change Section 15.10, page 188

The expression can be any SystemVerilog expression that evaluates to a positive integer value.

What constitutes a cycle is determined by the default clocking in effect (see Section 15.11). If no default clocking has been specified for the current module, interface, or program then the compiler shall issue an error.

Example:

## 5; // wait 5 cycles (clocking events) using the default clocking

## (j + 1); // wait j+1 cycles (clocking events) using the default clocking

The execution of a cycle delay statement is dependent upon the clocking event of the default clocking in effect. When the program execution reaches a cycle delay statement, the execution continues if there is a clocking event. Otherwise, the execution waits until the occurrence of a clocking event. For example,

module cpu( interface y );

...

default clocking bus @(posedge clk);

initial begin

a = b;

## 5; // delay statement (1)

c = d;

## 0; // delay statement (2)

e = f

...

end

endmodule

In the example above, when delay statement (1) is reached, it waits for next five clocking events of (posedge clk). When the execution reaches delay statement (2), the execution continues to the next statement if the clocking event (posedge clk) has occurred in the current time unit. Otherwise it waits, until the clocking event occurs and then continues to the next statement.