Change Section 3.7, page 12

SystemVerilog includes a string data type, which is a variable size, dynamically allocated array of bytes., which is an ordered collection of characters. The length of a string variable is the number of characters in the collection. Variables of type string are dynamic as their length may vary during simulation. A character may be read from a string variable by indexing the variable from 0 to N-1, where N is the length of the variable. Reading a character of a string variable yields a byte. SystemVerilog also includes a number of special methods to work with strings.

Verilog supports string literals, but only at the lexical level. In Verilog, string literals behave like packed arrays of a width that is a multiple of 8 bits. A string literal assigned to a packed array of an integral variable of a different size is either truncated to the size of the variable or padded with zeroes to the left as necessary.

In SystemVerilog string literals behave exactly the same as in Verilog However, SystemVerilog also supports the string data type to which a string literal can be assigned. When using the string data type instead of an integral variable, strings can be of arbitrary length and no truncation occurs. Literal strings are implicitly converted to the string type when assigned to a string type or used in an expression involving string type operands.

Variables of type string can be indexed from 0 to N-1 (the last element of the array), and they can take on the special value “”, which is the empty string. Reading an element of a string yields a byte.