System Verilog
		Testbench donation
		Open Review Issues
	Short name:	Description:	Resolution:
REV-1	$cast_assign	Static casting in SV? Why not a compiler issue instead of call?
REV-2	Array shorthand	Conflict with existing call
REV-3	Built-in string methods	Resolve class versus task syntax
REV-4	Forward reference with typedef	General implication
REV-5	Extern withdrawal	Impact
REV-6	Class issues	super/extends, local/private, virtual, protected etc...
REV-7	General use of Class	How general
REV-8	Virtual class vs interface	How do these relate
REV-9	Predefined constants	Keywords versus pre-defined constants
REV-10	Mailboxes	Mailbox and semaphores vs channels and queues in SV
REV-11	Mailboxes	Implemented as classes
REV-12	Program block	Reconcile with verilog module
REV-13	Clocking_domain	ports defined in multiple clock domains: questions of out1 = 1 and d1.out = 1 (out1 defined in two domains)