[sv-ec] solve before and arrays

From: Daniel Mlynek <danielm@aldec.com.pl>
Date: Wed Jan 30 2013 - 02:33:10 PST
LRM defines restrictions for solve before:
1) "The variables shall be integral values."
2) solve before must be used on the constraint_block_item syntax level - 
so it cannot be nested in other operators (if, -> foreach)

Because of this it is important to write solve before on all dynamic 
array elements (see xample at the end)
Does the first limitation still valid or it should be removed changed? 
Which types can be used in solve before (note I've found a mantis for 
classes only http://www.verilog.org/mantis/view.php?id=2999 )  what 
about other types which can be rand: fixed size arrays, unpacked struct

    class C;
       rand bit arr1[];
       rand bit[3:0] arr2[];
       constraint cc{
           solve arr1 before arr2; //illegal bcos item used solve before
    has to be integral types
         foreach (arr1[i]){
             solve arr1[i] before arr2[i]; //illegal bcos solve befor
    cannot be nested in foreach
             arr1[i] -> arr2[i]==0;
         }
       }
    endclass

    module top;
         C c=new;
         int dist1[int][int];
         int dist2[int][int];
       initial begin
         c.arr1=new[3];
         c.arr2=new[3];
         repeat(1000) begin
           assert (c.randomize) else $fatal("test failed");
           foreach (c.arr1[i])begin
               dist1[i][c.arr1[i]]++;
             dist2[i][c.arr2[i]]++;
           end
         end
         $display("dist1 %p", dist1);
         $display("dist2 %p", dist2);

       end
    endmodule

DANiel

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Received on Wed Jan 30 02:33:30 2013

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