Sometime between SystemVerilog 3.1a and 1800-2005, the BNF for a clocking _decl_assign was changed from
clocking_decl_assign ::= signal_identifier [ = expression ]
to
clocking_decl_assign ::= signal_identifier [ = hierarchical_identifier]
does anyone remember why?
But the LRM text (14.3) still refers to hierarchical_identifier
Filed as 0003982<http://www.eda.org/svdb/view.php?id=3982>
Dave Rich
Verification Technologist
Mentor Graphics Corporation
[Description: Description: Twitter-32]<http://www.twitter.com/dave_59> [Description: Description: Technorati-32] <http://go.mentor.com/drich>
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