Re: [sv-ac] Re: [Bulk] [sv-ec] Assertions & Covers in classes?

<There might be some challenging questions to answer about the
lifetime of the things being sampled in your properties.>
The real issue with those suggestions is the dynamic creation / kill of
class and virtual interface instances.
That is why they are not allowed, and I seriously doubt that the sv-ac
committee would allow it, as there are other issues that need to be
resolved.
Ben SystemVerilog.us

On Fri, Nov 5, 2010 at 3:21 PM, Jonathan Bromley
<jonathanbromley@ymail.com>wrote:

> Cliff,
>
>
> An interesting topic came up this week in a verification training class.
>>
>> Has any consideration been give to adding assertions and cover statements
>> to classes?
>>
>> The assertions and covers could be quite useful in a scoreboard setting
>> since the statements have rather powerful temporal speicfication
>> capabilities. One would still need to access signals via a virtual
>> interface, but it could be quite useful.
>>
>
> This certainly does come up in user discussions from time to time.
>
> Temporals in 'e' *can* (indeed, must) live in classes, and yes, it's
> useful.
> I don't know whether Vera offers similar features.
>
> I'm not sure what the formal folks would have to say about it, though.
> There might be some challenging questions to answer about the
> lifetime of the things being sampled in your properties.
> --
> Jonathan Bromley
>
>
>
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