[sv-ec] issue with virtual interfaces and mixed continous and procedural wrties to variable

In attached code signal sig_read is driven by both procedural assign via
virtual interface and continous assign via port connection
Should it be error in simulator (variables cannot be driven by mixture of
procedural and continuous assignmenr)?
if not then How should be the value of sig_read in such case resolved?
In below code value sig_read should be always == z or it should be == 1 at
the eof???
Is it defined in LRM? Where?
 
 
interface iface;
 logic sig_read;
endinterface
 
module dut(output reg read);
initial read = 1'bz;
initial #1 read <= 1'bz;
endmodule
 
class C;
 virtual iface vi;
 function drive;
  vi.sig_read<=1; //<<<<<procedural drive to top.iface_i.sig_read
 endfunction
endclass
 
module top;
 iface iface_i();
 dut uut(iface_i.sig_read); //continous assign to top.iface_i.sig_read
 C c =new();
 initial begin
 $monitor(iface_i.sig_read, uut.read);
  c.vi=iface_i;
  #1 c.drive();
  #1;
 end
endmodule
 

 
 
DANiel

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