[sv-ec] covergroup bins using wildcard in ranges

From: Daniel Mlynek <daniel.mlynek@aldec.com.pl>
Date: Tue Mar 23 2010 - 08:06:55 PDT

Please consider example like below. Wildcards are used in ranges which is
not explicitly forbidden by LRM. But LRM also does not defines how such code
should work.
Any ideas? Maybe it should be forbidden ?
 
module top;
 bit [3:0] a;
 covergroup g1;
  coverpoint a
  {
   wildcard bins wb1[] = {[4'bzz01:4'b0zzz]};
  }
 endgroup
 
 g1 g1_1 = new();
 
endmodule
 
DANiel

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Received on Tue Mar 23 08:07:15 2010

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