RE: [sv-ec] Typo in 10.9.1 Array assignment patterns

http://www.verilog.org/mantis/view.php?id=2977

-----Original Message-----
From: Karen Pieper [mailto:karen_l_pieper@yahoo.com]
Sent: Tuesday, February 09, 2010 7:13 PM
To: Neil.Korpusik@Sun.com; Daniel Mlynek
Cc: sv-ec@eda.org
Subject: Re: [sv-ec] Typo in 10.9.1 Array assignment patterns

Please make sure there is a mantis for this so we don't loose it.

Karen

----- Original Message ----
From: Neil Korpusik <Neil.Korpusik@Sun.com>
To: Daniel Mlynek <daniel.mlynek@aldec.com.pl>
Cc: sv-ec@eda.org
Sent: Mon, February 8, 2010 1:42:19 PM
Subject: Re: [sv-ec] Typo in 10.9.1 Array assignment patterns

This is an Editorial issue that can be assigned to the Editor of the next
version of the LRM.

On 02/08/10 04:56, Daniel Mlynek wrote:
> In chapter "*10.9.1 Array assignment patterns" **there is :*
>
> *int *unpackedints [1:0] = '{1'b1, 1'b1};
>
> while there should be:
>
> * *
>
> *int *unpackedints [1:0] = '{1'b1, 1'b1};
>
>
> DANiel
>
>
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