RE: [sv-ec] class process

From: Daniel Mlynek <daniel.mlynek@aldec.com.pl>
Date: Tue Feb 02 2010 - 05:40:28 PST

state is used later in context of type:
function state status();

state has to be typedef

DANiel

  _____

From: Jonathan Bromley [mailto:jonathan.bromley@verilab.com]
Sent: Tuesday, February 02, 2010 2:30 PM
To: Daniel Mlynek
Cc: sv-ec@eda.org
Subject: Re: [sv-ec] class process

On Tue, Feb 2, 2010 at 2:10 PM, Daniel Mlynek <daniel.mlynek@aldec.com.pl>
wrote:

I've added below note to mantis:
http://www.verilog.org/mantis/view.php?id=2956
 
 What means below definition in class declaration
enum state { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED };
 
should it be changed to :
typedef enum { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED } state ;

I think you'll find it's a member variable declaration, not a typedef.

You are of course right that the syntax is incorrect; "state"
should be at the end.

-- 
Jonathan Bromley
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Received on Tue Feb 2 05:40:50 2010

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