RE: [sv-ec] What is meant by "simple edge"?

Hi, 

>    // This first line of code is nothing to do with
>    // the clocking.  It's only here to ensure that
>    // the first @(ck2) takes us to a posedge, for
>    // the sake of the example.
>    @(negedge clk) #1;  // get to just after negedge
> 
>    @(ck2);  // get to a posedge
>    ck2.some_output <= 1'b1;  // takes effect on next negedge
>    @(ck2);  // get to the next negedge
>    ck2.some_output <= 1'b0;  // now?  one whole cycle later?
> 
> Now we have two synchronous drives.  The first (to 1'b1) was
> launched at the posedge and will mature at the following negedge.
> The second (to 1'b0) was launched at that same negedge, and 
> will mature on a negedge.  So:
> 1) On which negedge will the second drive mature? 
>    The current one, or the next one?

I am not well versed in clocking blocks, but I would interpret the LRM to mean "the current one".

> 2) Assuming the code performs a drive to the output 
>    on each @(ck2), there will surely be two drives
>    maturing at each negedge (and none at each posedge).
>    This doesn't sound either useful or meaningful.

But that is because of your assumption.
However, if my clocking event is double-edged and my output is single-edge triggered, then I would probably not drive the output on each clocking event, but rather on each alternate clocking event. One can always write examples that are "neither useful or meaningful". But that does not mean that there are not other examples that are not so.

Regards,
Shalom
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