RE: [sv-ec] What is meant by "simple edge"?

Shalom's example is indeed legal. The semantics are that input clockvars are sampled 1step before the edge (posedge/negedge) of clk, and output clockvars are driven on the negedge of clk. Note that the input/output skew specification does not alter the event used when applying the @ operator to the clocking block. Hence, @(ck2) is synonymous with @(clk). This is the situation that the "simple edge" wording was trying to avoid, but not because it is illegal; rather to explain the semantics of the simple case.

        Arturo

-----Original Message-----
From: owner-sv-ec@eda.org [mailto:owner-sv-ec@eda.org] On Behalf Of jonathan.bromley@doulos.com
Sent: Wednesday, August 12, 2009 3:01 PM
To: Bresticker, Shalom
Cc: sv-ec@eda.org
Subject: RE: [sv-ec] What is meant by "simple edge"?

Shalom,

> The clocking event may specify both edges, as in this example from the
LRM:
>
> clocking ck2 @(clk); // no edge specified!
>   default input #1step output negedge; // legal
>   input ... ;
>   output ... ;
> endclocking

Hmmmm..... Can anyone shed any light on what that
could possibly mean?  Let's try to use it...

  @(negedge clk) #1;  // get to just after negedge
  @(ck2);  // get to rising edge
  ck2.some_output <= 1'b1;  // takes effect on next negedge
  @(ck2);  // get to negedge
  ck2.some_output <= 1'b0;  // now?  one whole cycle later?

Surely this is precisely the situation that the "simple edge"
wording was intended to avoid, and the example must be wrong?
--
Jonathan Bromley
Consultant

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