RE: [sv-ec] What is meant by "simple edge"?

The clocking event may specify both edges, as in this example from the LRM:

clocking ck2 @(clk); // no edge specified!
  default input #1step output negedge; // legal
  input ... ;
  output ... ;
endclocking 

The wording of the comment "no edge" could be confusing, as also whether the text wording "a simple edge" or as proposed "simply an edge" applies to the @(clk) form.

Shalom

> -----Original Message-----
> From: owner-sv-ec@server.eda.org 
> [mailto:owner-sv-ec@server.eda.org] On Behalf Of 
> jonathan.bromley@doulos.com
> Sent: Tuesday, August 11, 2009 10:50 AM
> To: sv-ec@eda.org
> Subject: RE: [sv-ec] What is meant by "simple edge"?
> 
> > like "When the clocking event specifies simply an edge, and no delay
> > control, the skew becomes the specific edge of the clocking signal."
> 
> Or, perhaps, "specified".  And presumably the specified skew edge 
> can only be the edge opposite to that of the clocking event?
> -- 
> Jonathan Bromley
> 
> 
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