RE: [sv-ec] FW: continuous assignemts

 

I think that would be illegal as there are multiple drivers: 1 continuous assign
and 1 procedural assign stmt.

Francoise
    '
-----Original Message-----
From: David Jones [mailto:djones@xtreme-eda.com] 
Sent: Wednesday, July 22, 2009 10:53 AM
To: Rich, Dave
Cc: Francoise Martinolle; sv-ec@eda.org
Subject: Re: [sv-ec] FW: continuous assignemts

How about:

interface foo;
reg some_var;

  assign some_var = ...;
endinterface

module bar;
  foo ifoo();

virtual interface foo_h;

initial begin
  foo_h = ifoo;
  foo_h.some_var = 1;
end
endmodule

I haven't reviewed the chapter on interfaces recently, so I'm not sure if it's legal to deference an untyped virtual interface handle.
However, we have here two assignments to some_var, one of which cannot be readily discerned without some heavy dataflow analysis (in the general case).

Has this case been considered?

On Wed, Jul 22, 2009 at 10:38 AM, Rich, Dave<Dave_Rich@mentor.com> wrote:
> There are no restrictions on these types other than for any other variables.
> (i.e. multiple drivers) There are restrictions on members of class 
> vars and virt. intf. vars. (limited to procedural contexts).
>
>
>
> ________________________________
>
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] 
> On Behalf Of Francoise Martinolle
> Sent: Wednesday, July 22, 2009 7:10 AM
> To: sv-ec@server.eda.org
> Subject: [sv-ec] FW: continuous assignemts
>
>
>
> Are continuous assignment on class vars and virtual interface vars allowed?
>
>
>
> Francoise
>
>        '
>
>
>
> ________________________________
>
> From: Bresticker, Shalom [mailto:shalom.bresticker@intel.com]
> Sent: Wednesday, July 22, 2009 8:01 AM
> To: Francoise Martinolle
> Subject: RE: continuous assignemts
>
> I did not find such text.
>
>
>
> Shalom
>
>
>
> ________________________________
>
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] 
> On Behalf Of Francoise Martinolle
> Sent: Monday, July 20, 2009 11:55 PM
> To: sv-ec@server.eda.org
> Subject: [sv-ec] continuous assignemts
>
> Where is the text in the LRM which disallow continuous assignments to 
> class variable handles or
>
> virtual interface variables.
>
> I see that virtual interface variable are not allowed on port 
> expression which makes me think that
>
> continuous assignment to them are not legal.
>
>
>
> Francoise
>
>        '
>
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