[sv-ec] Mantis 2575

Is the following legal and should it be added to Mantis 2575 (asked 
by Mantis 2608)

WAS:
class vector #(parameter width = 7);
endclass

vector #(3) v = new;
initial $display (v.width);

PROPOSED:
class vector #(parameter width = 7);
endclass

vector #(3) v = new;
initial $display (v.width);

vector v2 = new;    // Legal - uses default parameter width = 7
initial $display (v.width);

vector #() v3 = new;   // Legal - uses default parameter width = 7 
-OR- // Illegal - specifying empty parameter value not permitted
initial $display (v.width);

Regards - Cliff

----------------------------------------------------
Cliff Cummings - Sunburst Design, Inc.
14314 SW Allen Blvd., PMB 501, Beaverton, OR 97005
Phone: 503-641-8446 / FAX: 503-641-8486
cliffc@sunburst-design.com / www.sunburst-design.com
Expert Verilog, SystemVerilog, Synthesis and Verification Training


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