Re: [sv-bc] RE: [sv-ec] Case @*

From: <jonathan.bromley_at_.....>
Date: Tue May 19 2009 - 02:44:49 PDT
Daniel

>> However, in this particular example, the question is whether there 
>> would be an initial change in i that triggers the always procedures. 

> OK so we can change the code by adding #0 : "initial #0 i = 0;"

Urrrrgh!!!!!!  That makes a nasty piece of code even more nasty!

>> This also occured in OVL and was reported in Mantis 2174 and 2426, 
>> the latter filed by you.

> Yes that is true - I just wanted to fwd this issue to commitee as I 
> hit this one once again - maybe correct behaviour can be explained 
> in LRM as user have problems with such codes

I don't think the LRM is the right place to say such things;
it should not attempt to be an instruction book.
The user code here is just plain wrong, for several reasons
that are (or, at least, ought to be) very well known in the
Verilog community:

1) It is usually unsafe to rely on time-0 events.  It's far
   too easy to get races between updates and event-waits
   at time 0.
2) Using a module-level variable as the loop counter in a 
   procedural "for" loop is almost always a really stupid 
   thing to do.  There is a huge risk of unwanted interaction
   between loops in multiple processes - have you noticed how
   every loop counter is called "i" or "j"?  Users can easily
   and completely protect themselves against this by using a
   locally-declared loop counter, either in a named block or
   (in SV) in the loop itself, and there is no excuse for
   doing otherwise.

Both these points are well-documented in many books, training
courses and presentations.  It's kinda disappointing to see
a major FPGA vendor making use of this poor style (although,
of course, without seeing the full code it is unfair to
criticize too much).
-- 
Jonathan Bromley
Consultant

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Received on Tue May 19 03:30:33 2009

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