Re: [sv-ec] Ballot issue #182, Mantis 2514: Out of block constraints

Hi,

I'll weigh in with an opinion since I am one of the ones to pressure the
vendore to support unimplemented constraint blocks.

I would accept a warning (that can be disabled) but not an error. I need out
of constraint blocks to allow tests to inject constraints without disrupting
the class hierarchy.

In most of my classes, I prototype a TEST constraint. That way, a test can
add constraints as needed.

Take Care,
Mike

On Tue, Apr 21, 2009 at 8:16 AM, Daniel Mlynek <daniel.mlynek@aldec.com>wrote:

> Why not add both keywords:
>  pure constraints
> and
>  extern constraints
>
> Same as it was finnaly cleared for methods
>
> DANiel
>
> -----Original Message-----
> From: owner-sv-ec@server.eda.org [mailto:owner-sv-ec@server.eda.org] On
> Behalf Of jonathan.bromley@doulos.com
> Sent: 21 kwietnia 2009 14:01
> To: sv-ec@eda.org
> Cc: Bresticker, Shalom; Rich, Dave
> Subject: RE: [sv-ec] Ballot issue #182, Mantis 2514: Out of block
> constraints
>
> [Dave Rich, concerning a constraint
> prototype that lacks an implementation]
>
> > This is either a compile/elaboration error, or it is not an error.
>
> Right.  It seems that implementations have converged on the permissive
> approach - I'm guessing there has been some user pressure there - and the
> meaning is fairly clear; an unimplemented constraint is presumably the same
> as
>  constraint foo {1;}
> and has no effect.  This all seems quite sensible to me, but I agree with
> the existing implementations: it likely represents a user oversight, and
> should evince a warning.
>
> However, it's also evident that different tools regard the constraint
> prototype in different lights.  One simulator clearly thinks of the
> constraint prototype as being, in effect, a "pure virtual" that is OK in an
> abstract class but should be overridden in any concrete derived class.
> Other simulators give the warning for an unimplemented constraint prototype
> even when it appears in an abstract class.  I'm inclined to support the
> "pure virtual" position, but it may have repercussions I haven't thought
> of.
> In particular, it tangles the syntax of derived-class constraints with that
> of out-of-block constraints.
>
> Advice please?
> --
> Jonathan Bromley
> Consultant
>
> Doulos - Developing Design Know-how
> VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project
> Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW,
> UK
> Tel:  + 44 (0)1425 471223                       Email:
> jonathan.bromley@doulos.com
> Fax:  +44 (0)1425 471573                        http://www.doulos.com
>
>
> ----------------------------------------------------------------------------
> ----
> Doulos Ltd is registered in England and Wales with company no. 3723454 Its
> registered office is 4 Brackley Close, Bournemouth International Airport,
>        Christchurch, BH23 6SE, UK.
>
> This message may contain personal views which are not the views of Doulos,
> unless specifically stated.
>
>
>
> --
> This message has been scanned for viruses and dangerous content by
> MailScanner, and is believed to be clean.
>
>
> --
> This message has been scanned for viruses and
> dangerous content by MailScanner, and is
> believed to be clean.
>
>

-- 
This message has been scanned for viruses and
dangerous content by MailScanner, and is
believed to be clean.