Table 7-1 in the ballot draft says that string replication looks like {multiplier{Str}} and describes it as though there can be only one string expression in the inner braces. However, for consistency with ordinary Verilog replication it should surely be {multiplier{Str1, Str2, ..., StrN}} The BNF (A.8.1) permits the latter form, and so does at least one simulator. Is it reasonable to modify Table 7-1 accordingly, or is that outwith the terms of the ballot revision? -- Jonathan Bromley Consultant Doulos - Developing Design Know-how VHDL * Verilog * SystemVerilog * SystemC * PSL * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: + 44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 http://www.doulos.com -------------------------------------------------------------------------------- Doulos Ltd is registered in England and Wales with company no. 3723454 Its registered office is 4 Brackley Close, Bournemouth International Airport, Christchurch, BH23 6SE, UK. This message may contain personal views which are not the views of Doulos, unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Apr 16 14:12:25 2009
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