[sv-ec] Question about interface ports on modules

Hi folks,

There is a restriction in 23.3.3.4 (that has been around since Accellera SV) that any interface ports of a module must be connected to an interface instance at a higher level of hierarchy. This would seem to preclude creating an RTL design with interface ports at the top level. What is the reason for this restriction? Am I misunderstanding the meaning here?

More specifically, for simulation one would normally have a testbench that instantiates the DUT and connects the interface ports - no problem there. However, many other tools (synthesis, formal, back-end, etc.) read in just the DUT. Would those tools be required to reject a design with top-level interface ports?

Thanks,
Mike


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