[sv-ec] module parameter assigned to specify parameter

Hello,

According to Section 4.10.3 of the Verilog LRM 1364-2005
"The value assigned to a specify parameter can be any constant expression."

Again,as per table 4.7 of the same section
Parameters (module parameter) "May not be used inside specify blocks"

Now consider the following example:

specify
   specparam si = si1;
endspecify

where, 
parameter shortint signed si1 = -3; // declared within the module scope

The standard tools are behaving differently for the above case.
While some passes,others are giving error or warning.

What should be the correct behaviour?

Thanks,
Kakoli





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