[sv-ec] variable initialization at declaration

LRM:
" In Verilog, an initialization value specified as part of the declaration
is executed as if the assignment were made from an initial block, after
simulation has started. In SystemVerilog, setting the initial value of a
static variable as part of he variable declaration (including static class
members) shall occur before any initial or always blocks are started."

Is initialization really a part of declaration - if so then newly declared
identifier is visble after ';', and in initialization phase this identifier
remains not declared. I mean what should happened for below code:
 
module top;
    parameter p=123;
    initial begin : _label
        int p=p; //this is circular illegal assignment p=p, or at the moment
of initialization p from outer scope is still visible?
        $display(p);    
    end
endmodule
 
DANiel

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