RE: [sv-ec] Upward referencing rules question

From: Steven Sharp <sharp_at_.....>
Date: Mon Feb 11 2008 - 16:22:22 PST
>From: "danielm" <danielm@aldec.com.pl>

>So if this reference found as first wouldn't be a variable - then search
>should proceed? below example shold work and print '5' ? :

Yes.  It must work this way, because this is how Verilog has always
worked for this case.


Steven Sharp
sharp@cadence.com


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Received on Mon Feb 11 16:22:54 2008

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