Re: [sv-ec] RE: [sv-ac] Seuence Instance passed as an argument to sequence

From: Surya Pratik Saha <spsaha_at_.....>
Date: Wed Jan 30 2008 - 22:00:29 PST

Hi,
As per SV LRM 1800-2005, (section 17.6 Declaring sequences):

An actual argument can replace any of the following:
 Identifier
 Expression
 Event control expression
 Upper delay range or repetition range if the actual argument is $

A sequence instance is not part of normal expression. So as per LRM the case is illegal.

Regards
Surya

-------- Original Message  --------
Subject: [sv-ec] RE: [sv-ac] Seuence Instance passed as an argument to sequence
From: Korchemny, Dmitry <dmitry.korchemny@intel.com>
To: Sarani Roy <sarani@cal.interrasystems.com>, sv-ec@eda.org, sv-ac@eda.org
Date: Wednesday, January 30, 2008 6:22:38 PM

Yes, this is correct.

Dmitry.

-----Original Message-----
From: owner-sv-ac@server.eda.org [mailto:owner-sv-ac@server.eda.org] On
Behalf Of Sarani Roy
Sent: Wednesday, January 30, 2008 2:21 PM
To: sv-ec@server.eda.org; sv-ac@server.eda.org
Subject: [sv-ac] Seuence Instance passed as an argument to sequence

Hi,

Is this a valid scenario:

sequence s1;
 @(posedge clk) irdy ##1 !trdy ##1 !devsel;
 endsequence

 sequence seq (s,trans,grant,n);
 @(posedge clk) s ##1 trans ##1 grant[*n];
 endsequence

 property p1;
 @(posedge clk)
 reset |=> seq(s1,next_state==3'b111,stop,4) ##1 frame[*2];
 endproperty
 
 assert property(p1);

Most of the standard tools are passing.

Thanks,
Sarani



  

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