> See http://www.eda-stds.org/sv-ec/hm/4341.html . > > It seems that nothing was done about it. OK, maybe it has to remain as an erratum, since 1742 didn't make it onto our do-before-the-deadline list. I would nevertheless appreciate clarification of the two other points I mentioned, if anyone knows the intent. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Thu Jan 10 04:06:17 2008
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