Re: [sv-ec] clocking blocks and `delay_mode_zero (or similar)

Neil Korpusik wrote:
> Hi Gord,
> 
> One thing that I just noticed is that the description of these
> compiler directives only mentions modules. It doesn't say
> anything about program blocks. My biggest concern is
> with clocking blocks contained within program blocks. For
> clocking blocks contained within programs I would not expect
> `delay_mode_zero to have any effect on clocking block input and
> output skews. In particular, it wouldn't make sense to change
> the definiton of a #1step nor #0 clocking block delay.
> 
> When clocking blocks are used in modules it just might make sense
> to honor these compiler directives.

But what does "honoring" them mean?  That was the core part of
my question.  Does that mean changing the output and input skews
to 0?  Does "0" here mean the same as the #0 skew semantics
of the clocking block?  Would this apply to both reg and
net skews?

I really don't know what the answers should be here; I am
primarily looking for any answer that is agreeable and
sensible to the users.

Gord.

-- 
--------------------------------------------------------------------
Gordon Vreugdenhil                                503-685-0808
Model Technology (Mentor Graphics)                gordonv@model.com


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