RE: [sv-ec] reference to class definition nested in module/program /interface

Mirek,

You've should look back at the e-mail threads on the sv-bc for the last
3 months.

The alternative for accessing types across the hierarchy is to put your
types in packages.

The key thing that Verilog has that none of the other OO languages you
mention have is parameterized hierarchical elaboration. It is
essentially a distinct form of object orientation that gives you the
ability to do hierarchical references which the other languages don't
have. 

The key thing that Verilog doesn't have that that SV adds is a type
system similar to the other OO languages you mention. Problems come in
is when you try to blend the two systems.

The easiest to problem to explain is the parameterized elaboration. If
you have:

module mod #(parameter N=2)();

typedef int arr[N];

endmodule

and then you try to 

module bod;

mod::arr A;

endmodule

module top;

mod  #(3); m1()
mod  #(4); m2()
bod bod();
endmodule


Which instance of mod would you be referring to in bod?

Then there's

module bod;

top.m1.arr A;

endmodule

The problem here is compilation order dependencies. In general, Verilog
does not allow you to refer to hierarchical references to parameters in
declarations because it needs to impose a strict ordering of parameter
overrides during elaboration. Interface types are a special case because
the port connection imposes an ordering that the elaboration process can
follow.

Another problem that is harder to explain is the fact that Verilog
allows modules to be referenced before being compiled. Even with that
flexibility, Verilog still requires simple identifiers to be declared
before referenced. This is a parsing requirement that came from Pascal,
one of Verilog's progenitors. There is even a stronger parsing
restriction for types, which I am currently writing up a mantis issue
on, which we agreed to in a recent face-to-face meeting on this subject,
which requires a type identifier to be known to be a type before it can
be referenced.

There are two ways to accomplish this across the hierarchy: one is
through packages, and the other is though hierarchical type
parameterization.

for example, through packages
package pkg;
typedef struct {int A;} s_t;
endpackage

module A();

pkg::s_t i;

endmodule

module B#(type T=int)();

pkg::s_t i;

endmodule

module top;

A a();
B b();

initial a.i=b.i; // legal assignment

endmodule

Through hierarchical type parameterization.


module A#(type T=int)();

T i;

endmodule

module B#(type T=int)();

T i;

endmodule

module top;

typedef struct {int A;} s_t;

A #(s_t) a();
B #(s_t) b();

initial a.i=b.i; // legal assignment

endmodule



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