[sv-ec] hierarchical references into programs

Hi,

I corresponded with Gord a few months ago about the following issue:

All the references are to Draft 4:

23.5 says,
"Calling program tasks or functions from within design modules is
illegal and shall result in an error."

(Probably the word 'design' should be stricken as there is no concept of
'design modules' and 'non-design module'.

23.3 says, 
"References to program signals from outside any program block shall be
an error."

23.6 says,
"The set of program definitions and instances define a space of
programwide data, tasks, and functions that is accessible only to
programs."

Thus, in Gord's words: "The LRM does not allow ANY hierarchical
references from modules to programs."

Yet, 22.10 says,
"By binding a program to a module or an instance, the program becomes
part of the bound object. The names of assertion-related declarations
can be referenced using the SystemVerilog hierarchical naming
conventions."

In the context, the meaning seems to be that the 'assertion-related
declarations' (whatever that means) are in the program, and the
hierarchical reference is from outside the program to inside the
program.

This is illegal, however.

Thus, this statement in 22.10 should be changed. Gord suggests adding
the following sentence in 22.10:

"Hierarchical references to an item in a bound instance are permitted
following normal hierarchical naming rules."

Thanks,
Shalom
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