RE: [sv-ec] forward declaration of a parameterized classes

Gordon Vreugdenhil:
> Mark, neither Don's example nor my agreement included
> the defaults.  They aren't needed and in fact, I would
> be fine with having just:
>     typedef class T #();
> to indicate that "T" is a forward to a parameterized class.
> 
> I don't think that it is a good idea to allow forwards
> by just using the type name.

But the current LRM clearly allows forwards by just the type name.
That is in fact the reasons for forward typedef, to specify that
the name is a type name. 

There is currently no syntax for a forward typedef any other way.
If we were to change the LRM to only allow forward typedefs to
parameterized classes with one of your proposed syntaxes, then 
this would not be backwards compatible with a great deal of 
System Verilog code that already exists.

I see absolutely no reason to make this change. The syntax is
confusing. It does not clarify intent, it only makes things 
more confusing for the user.

typedef class C #();

is a forward declaration of a parameterized class 'C', but

typedef C #() D;

is a declaration of a type 'D' which is class 'C' with default
parameter values. This is extremely confusing.

I can see no reason for making a change like this. It adds nothing
but confusion to the language. If it is extremely important that
tools be able to check the parameter overrides on parameterized class
references at parse time, then they can clearly do this already
with the existing language. A type that is forward typedefed must 
always be defined in the same scope. All a tool has to do is wait 
until the actual class is defined and then check all the references 
to the type to see if the parameter overrides are valid.




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