I have created Mantis 2021 to address this, and uploaded a (very short) proposal which I believe is ready for vote. > whilst scanning the Draft 3a LRM for editorial questions > I noted what I suspect is an oversight from Mantis 890. > > At the head of page 284, clause 14.5 says: > > In a clocking block, any expression assigned to a > signal in its declaration shall be an expression > that would be legal in a port connection to a port > of any of the directions specified in the declaration. > For example, it would be illegal to assign an inout > signal an expression in its declaration that would be > illegal in a port connection to an inout port. > > This restriction is much too severe for inout clockvars. > In clocking blocks, "inout" is shorthand for "input output" > and does NOT require a net, as does a true inout port. The > only requirement that the inout clocking signal must meet > is that it should be legal as the hi-conn of both an input > and an output port. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 Email: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated. -- This message has been scanned for viruses and dangerous content by MailScanner, and is believed to be clean.Received on Fri Sep 7 17:48:43 2007
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